An electrostatic discharge (ESD) protection element comprising diodes or resistance elements is used conventionally to protect the circuit elements in a semiconductor integrated circuit against ESD. Recently, ESD protection elements provided in a CMOS (Complementary Metal Oxide Semiconductor) integrated circuit have come to be replaced by MOS-type protection elements that utilize a parasitic bipolar operation and exhibit a lower resistance and a higher discharge capability than ESD protection elements comprising diodes or resistance elements. Such a MOS-type protection element is one that utilizes the snapback phenomenon of a MOSFET (MOS Field-Effect Transistor).
The ability to pass electric current is limited even in a MOS protection element that relies upon a parasitic bipolar device. In many cases protection performance will not meet the required level unless the width of the protection element is enlarged to 400 to 800 μm. In an integrated circuit, however, the arrangement of bonding pads usually imposes a limitation upon layout and often the MOS protection element must be made to fit in a stipulated area. For this reason, a method adopted in the art is to employ not a MOS protection element consisting of a single element but rather one having a plurality of small MOSFETs referred to as fingers having a width of 10 to 50 μm, arranging them in a direction (e.g., the horizontal direction) perpendicular to the direction of current flow, connecting them in parallel with one another and arranging the elements in the stipulated area in an efficient manner. To achieve this, one method is to commonly connect the sources and drains of the fingers to thereby connect the plurality of fingers in parallel with one another, and another method is to array small MOSFETs individually and connect them in parallel with one another (see Non-Patent Document 1, namely Tong Li, Ching-Han Tsai, Elyse Rosenbaum and Sung-Mo Kang, “Substrate resistance modeling and circuit-level stimulation of parasitic device coupling effects for CMOS I/O circuits under ESD stress”, Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 1998, 6–8 Oct. 1998, pp. 281–289).
FIG. 15 is a plan view illustrating an input protection element 101 that utilizes the snapback phenomenon of an NMOSFET, which is a conventional MOS-type projection element, FIG. 16 is a diagram illustrating a cross section taken along line A–A′ in FIG. 15 as well as an equivalent circuit thereof, and FIG. 17 a graph illustrating the operating characteristic of this MOS-type protection element, in which voltage applied to the protection element is plotted along the horizontal axis and current that flows into the protection element is plotted along the vertical axis. In the MOS-type protection element 101, a plurality of gate electrodes 103 extending in one direction are provided in parallel above a P-type substrate 102, and regions directly underlying the gate electrodes 103 in the surface of the P-type substrate 102 serve as channel regions 104. The areas between the channel regions 104 in the surface of the P-type substrate 102 define source regions 105 or drain regions 106, and the source regions 105 and drain regions 106 are arrayed in alternating fashion.
As a result of this structure, a plurality of MOSFETs 111 are formed and the source regions or drain regions of mutually adjacent MOSFETs 111 are connected in common. A plurality of contacts 107 are arrayed in a single row on the surface of respective ones of the source regions 105 and drain regions 106 in a direction along which the gate electrodes 103 extend. A guard ring 108 comprising a heavily doped p+ is provided in the surface of the P-type substrate 102 so as to surround the plurality of MOSFETs 111 and is connected to a ground wiring 109. The guard ring 108 is provided for the purpose of preventing latch-up. An input pad 110 is connected to the contact 107 formed on the surface of the drain region 106.
Referring to FIGS. 15 to 17, the operation of the MOS protection element 101 is described. When a surge current enters the input pad 110, the surge current flows into the drain region 106 via the contact 107, thereby raising the drain voltage. If the drain voltage exceeds the voltage indicated at Vt0 in FIG. 17, avalanche breakdown begins at the PN junction between the drain region 106 and channel region 104 and a substrate current flows. At this time a parasitic bipolar transistor is formed in which the source region 105 of each finger is the emitter, the P-type substrate 102, inclusive of the guard ring 108, is the base and the drain region 106 is the collector. Owing to the current that flows through the interior of the P-type substrate 102, a potential difference corresponding to the product of this current and the resistance of the P-type substrate 102 is produced in the P-type substrate 102 and the potential in the vicinity of the bottom surface of the source region 105 in the P-type substrate 102 rises relative to the guard ring 108. When the voltage applied to the MOS protection element 101 reaches Vt1, as shown in FIG. 17, the potential in the vicinity of the bottom surface of the source region 105 relative to the guard ring 108 becomes large enough, e.g., 0.7 V, to forward bias the PN junction between the source region 105 and channel region 104. The PN junction thus is forward-biased, a further current flows and a state of low resistance is obtained owing to conduction of the parasitic bipolar transistor. As a result, a larger current flows. This phenomenon is referred to as snapback, and the voltage Vt1 is referred to as snapback starting voltage or trigger voltage.
If it is attempted to perform an I-V measurement of the kind shown in FIG. 17 by means of an ordinary current-voltage measuring apparatus, measurement requires application of current for an extended period of time. Consequently, the DUT (Device Under Test) will be destroyed before the snapback state is attained. To measure the snapback phenomenon, therefore, usually a measurement apparatus referred to as a TLP (Transmission Line Pulser) is employed. This apparatus subjects the DUT to a rectangular current waveform having a duration on the order of 100 ns and reads the values of current and voltage of the DUT from a change in the voltage and current thereof. (By way of example, see Non-Patent Document 2, namely Barth, J. et al, “TLP calibration, correlation, standards, and new techniques [ESD test]”, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000, 2000 pp. 85–96.) In general, V=It2×1500 has been experimentally determined to be the relationship between breakdown current It2 [A] of a DUT measured with a TLP and breakdown voltage V [V] of the DUT measured by a human body model (HBM) test.
Non-Patent Document 3 (Christian Russ, Karlheinz Bock, et al., “Non-Uniform Triggering of gg-nMOSt Investigated by Combined Emission Microscopy and Transmission Line Pulsing”, Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 1998 pp. 177–186) states that since avalanche current is highly dependent upon the electric field applied to a PN junction, there is a high probability that snapback will occur in a MOS transistor from a corner where the electric field is strongest.
Further, Non-Patent Document 4 (Kwang-hoon Oh, et al., “Non-Uniform Bipolar Conduction in Single Finger NMOS Transistors and Implications for Deep Submicron ESD Design”, IEEE 01CH37167.39th Annual International Reliability Physics Symposium, Orlando, Fla., 2001 pp. 226–234) reports that in a process that uses a low-resistance substrate, there are instances where snapback occurs locally at random locations in a finger owing to statistical variations in the process.
In a single-finger protection element, as described above, a problem is that the element tends to be destroyed owing to current crowding. Further, there are instances where snapback voltage is too high and instances where breakdown occurs owing to application of excessive current to the element's own gate electrode. The inventions described in Patent Documents 3 and 4 (Japanese Patent No. 3157614 and Japanese Patent Kokoku Publication No. JP-B-8-24183, respectively) are inventions relating to such cases.
In Patent Document 3, as shown in FIG. 30, the impurity-doped region of a source area is provided with a resistor, and a gate electrode is connected to ground potential via this resistor, thereby preventing an excessive voltage from being impressed upon the gate voltage of the transistor.
As shown in FIG. 31, Patent Document 4 describes a structure in which the occurrence of electrostatic breakdown is prevented by forming notches in both sides of a source to thereby provide resistance and lowering the peak voltage of electrostatic stress at the boundary points between a field oxide film, gate electrode and source region or drain region where an electric field ascribable to application of static electricity tends to occur.
A MOS-type protection element comprising a plurality of fingers (namely a multifinger-type protection element) has the following problem: In multifingers, operation differs from finger to finger. This difference in operation can be explained as being ascribable to a difference in substrate resistance. More specifically, since the distance to the ground electrode (usually the guard ring) as seen from each finger differs, the substrate resistances, namely the base resistances of the parasitic bipolar transistors, differ from one another. As a result, owing to accumulation of electric charge after avalanche breakdown, a difference develops in the local voltage formed at the junction region between the source region and channel region of each MOSFET. Accordingly, the timings at which the parasitic bipolar transistors reach the snapback voltage differ and the timings at which the parasitic bipolar transistors turns on differ. In actuality, as shown in FIGS. 15 and 16, substrate potential is coupled to the substrate currents of the fingers and the substrate resistance differs depending upon the three-dimensional current route in each finger and the lateral substrate resistances within the fingers. Thus, the causes that lead to a difference is substrate resistance between fingers include complicated factors.
If a current flows into the PN junction on the drain side of a finger, namely the PN junction between the drain and channel regions, the potential difference at this PN junction comprises the major part of the potential difference within the finger and heat is therefore produced, mainly in the region of the PN junction. There is a positive correlation between the current and the junction temperature; the higher the temperature, the greater the current. In other words, if current concentrates in some of the fingers owing to process variations and structure, or if there are statistical variations in contact resistance and drain resistance within a finger and current concentrates in a specific finger or in a specific area of a finger, then this will trigger the occurrence of positive feedback in which the PN junction of the finger in which current has concentrated or in the specific region of the finger evolves heat, thereby raising the temperature and producing a further increase in amount of current. The heated portion will eventually melt. Consequently, the finger turned on first breaks down before other fingers are turned on, meaning that the advantages of the multifinger structure are not exploited.
A technique in which a protection element is provided with a trigger circuit to turn on a parasitic bipolar transistor in the protection element reliably has been disclosed (see Patent Document 1, namely U.S. Pat. No. 5,450,267). FIG. 18 is an equivalent circuit diagram illustrating this conventional protection element disclosed in Patent Document 1. As shown in FIG. 18, the conventional protection element is such that a current control switch 122 is connected to an input pad 121 into which a surge current flows. Further, the current control switch 122 is provided with an NMOS transistor 123 having its drain and source connected to the input pad 121 and to a ground electrode, respectively. The protection element is provided with a trigger circuit 124 in addition to the current control switch 122. The trigger circuit 124 is provided with an NMOS transistor 125 having its drain and source connected to the input pad 121 and to the gate of the NMOS transistor 123, respectively. When a surge current enters the input pad 121 of this conventional protection element, first the NMOS transistor 125 of the trigger circuit 124 turns on to apply a positive voltage to the gate of the NMOS transistor 123.
When the gate potential of the NMOS transistor 123 rises, a current starts flowing into the NMOS transistor 123, whereby avalanche breakdown tends to occur uniformly across the channel region. An advantage, therefore, is that snapback begins at a lower voltage.
As a result, NMOS 123 does not evolve heat locally, an excessively high voltage is not produced, safe turn-on is achieved and the surge current that entered the input pad 121 flows to the ground electrode.
However, the prior art described above involves the following difficulty: If the technique described in Patent Document 1 is applied to a protection element having a multifinger structure, e.g., if a trigger circuit is connected independently to each of the individual protection elements (fingers), there is the possibility that a protection element (an individual finger) will snap back and be destroyed by current crowding unless the device employs an arrangement in which the trigger circuit operates first (the present invention, described later, is equipped with such an arrangement).
On the other hand, if just one trigger circuit is provided and this single trigger circuit is connected to all of the multiple fingers, then, when only a specific finger snaps back, current will concentrate in this finger and it will be destroyed in a manner similar to the above.
A conceivable method of solving this problem is to connect the source of each finger to the gate of the neighboring finger (see Patent Document 2, namely U.S. Pat. No. 6,583,972). FIG. 19 is an equivalent circuit illustrating a multifinger-type protection element described in Patent Document 2, and FIG. 20 is a graph illustrating the operating characteristic of this MOS-type protection element, in which the voltage applied to the protection element and the current that flows into the protection element are plotted along the horizontal and vertical axes, respectively. In this protection element, as illustrated in FIGS. 19 and 20, n-number (where n is a natural number of 2 or greater) of fingers F1 to Fn are connected in parallel with one another between an input pad 131, to which ESD is applied, and a ground electrode 132. In each finger Fi (i=1 to n), a drain resistor Rdi (i=1 to n), NMOS transistor Ti (i=1 to n) and source resistor Rsi (i=1 to n) are connected in series in order from the input pad 131 to the ground electrode 132. The source resistor Rsk in the finger Fk [k=1 to (n−1)] is connected to the gate of NMOS transistor Tk+1 of the neighboring finger Fk+1. The source resistor Rsn of finger Fn is connected to the gate of NMOS transistor T1 of finger F1. Thus, all of the fingers are connected into a ring-shaped configuration as a whole.
When finger Fk snaps back, a current flows into source resistor RSk and a potential difference is produced. Since the intermediate point of the resistor Rsk is connected to the gate electrode of the neighboring finger Fk+1, the gate potential Gk+1 rises. Owing to the rise in gate potential, current begins to flow into the finger Fk+1. As a result, avalanche breakdown tends to occur uniformly across the channel region. This has the additional advantage of reducing the snapback voltage. Accordingly, the NMOS transistor Tk+1 of the neighboring finger Fk+1 turns on safely and finger Fk+1 snaps back. Owing to snapback of finger Fk+1, finger Fk+2 snaps back, and so on. When any single finger snaps back, all fingers snap back sequentially in a chain-like fashion. Thus, the method employed by this protection element is referred to as the “domino method” because all fingers snap back in a “domino effect” manner.
[Non-patent Document 1]
Tong Li, Ching-Han Tsai, Elyse Rosenbaum and Sung-Mo Kang, “Substrate resistance modeling and circuit-level stimulation of parasitic device coupling effects for CMOS I/O circuits under ESD stress”, Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 1998, 6–8 Oct. 1998, pp. 281–289
[Non-patent Document 2]
Barth, J. et al, “TLP calibration, correlation, standards, and new techniques [ESD test]”, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000, 2000 pp. 85–96
[Non-patent Document 3]
Christian Russ, Karlheinz Bock, et al., “Non-Uniform Triggering of gg-nMOSt Investigated by Combined Emission Microscopy and Transmission Line Pulsing”, Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 1998 pp. 177–186
[Non-patent Document 4]
Kwang-hoon Oh, et al., “Non-Uniform Bipolar Conduction in Single Finger NMOS Transistors and Implications for Deep Submicron ESD Design”, IEEE 01CH37167.39th Annual International Reliability Physics Symposium, Orlando, Fla., 2001 pp. 226–234
[Patent Document 1]
U.S. Pat. No. 5,450,267
[Patent Document 2]
U.S. Pat. No. 6,583,972
[Patent Document 3]
Japanese Patent No. 3157614
[Patent Document 4]
Japanese Patent Kokoku Publication No. JP-B-8-24183
In a MOS-type ESD protection element, as described earlier, usually the parasitic bipolar state that occurs locally in each finger spreads to all fingers, whereby all fingers attain a state of low resistance and snap back. As a result, ESD current can be caused to discharge stably. However, in a case where the parasitic bipolar state does not spread to all fingers, current concentrates in the region that that snapped back first in the fingers and this finger may be destroyed.
In the above-mentioned domino-type multifinger ESD protection element (Patent Document 2), the finger that snaps back first exhibits a snapback operation different from that of the other fingers that snap back sequentially thereafter because this finger has a gate potential that is ground potential. More specifically, in the finger that snaps back first, the parasitic bipolar state occurs locally in a region where the electric field at the drain end is strong. At this time current flows from the drain to the source of this MOS transistor but the gate potential thereof remains at ground potential. In other words, the circuit arrangement is such that in the finger that snaps back first, the electric field at the PN junction of the drain end is stronger than that of the other fingers; if a current flows, this electric field is strengthened further. Consequently, the parasitic bipolar state that occurs at the drain end does not readily spread to the regions of the other fingers and often current concentrates in the region in which the parasitic bipolar state occurred first.
By contrast, in the other fingers that snap back sequentially thereafter, the fact that the gate potential is initially elevated means that the parasitic bipolar state will readily spread to all fingers and a channel current will tend to flow uniformly over the entire region of fingers. As a result, all fingers attain the parasitic bipolar state and snap back substantially simultaneously. Thus, in the domino-type multifinger ESD protection element described above, a problem is that the finger that snaps back first tends to be destroyed.
In order to solve this problem, a method in which the gates of all fingers are connected together also is conceivable. FIG. 21 is a circuit diagram illustrating a conventional protection element in which the gates have thus been connected in common. As shown in FIG. 21, the gates of all fingers Fi (i=1 to n) of this conventional protection element are connected together and the respective sources of fingers are connected to the commonly connected gates via respective ones of diodes. As a result, when one finger has snapped back, the source potential of this finger rises, a voltage is applied to the gates of all fingers inclusive of this finger and all of the fingers snap back. With this method, however, there is an increase in the area of the layout because it is required that each finger be provided with a diode. Further, since all gates are interconnected, source potential is dispersed and eventually the highest electric potential is applied to the gate nearest the source whose potential has risen, namely the gate of the finger that has snapped back first. As a result, further current flows into the finger that snapped back first and current concentrates in this finger. In addition, in snapback of the other fingers, the fact that the operating speed of the diodes is slow means that the local current crowding in the finger that snapped back first cannot be suppressed and, hence, destruction of this finger cannot be prevented.
In a conventional multifinger MOS protection element having a shared source region (heavily doped n+ region), the snapback state is attained substantially simultaneously, in which the potentials at the base/collector PN junctions of each of the parasitic bipolar transistors affect one another via the substrate (P wells) owing to low resistance (i.e., as a result of substrate coupling). However, with the domino-type multifinger ESD protection element (see Patent Document 2), the multiple fingers are all such that their elements are isolated, as a result of which resistance rises and the effect of substrate coupling is diminished. This represents a problem.
Further, with the domino-type multifinger ESD protection element (see Patent Document 2), the source regions are split and a resistance element is inserted between the split source regions. A problem which arises is a larger layout area.
Accordingly, an object of the present invention is to provide a multifinger ESD protection element of reduced layout area in which it is possible to prevent destruction of a finger that snaps back first.